In recent years, a general-purpose SDRAM (Synchronous Dynamic Random Access Memory) is becoming popular that has a high-speed interface such as in a DDR2-SDRAM or a DDR3-SDRAM. Since the SDRAM is a general-purpose product, the specifications are defined such that the SDRAM has a large timing margin. On the contrary, a timing margin for a memory controller LSI (Large Scale Integrated Circuit) connecting to the SDRAM is very strict. A data strobe signal DQS is outputted in the same phase as a data signal DQn from a DDR2/DDR3-SDRAM. The data strobe signal indicates a timing for transmitting the data signal. Since the phase of the DQS and the DQn are the same, it is difficult to transmit the data signal under this condition.
In the above circumstances, an interface circuit needs to control the shifting of the phase of the data strobe signal by substantially 90°. For the substantially 90°-phase shifting control, a DLL (delay locked loop) circuit is used, for example. However, since the DLL has a large scale circuit, if many DLLs are installed, it increases an area or power consumption of the circuit.
On the other hand, a delay circuit can be provided instead of the DLL. However, it is difficult to optimize a delay amount by the delay circuit. For example, even if the amount is set to a value estimated at the designing of the circuit, the optimal setting might not be achieved due to an unevenness in quality of the interface circuit, temperature change, power voltage change or the like.
Another method generates a calibration pattern for a DDR2/DDR3-SDRAM at power-on by using the delay circuit which is able to change the delay amount, and controls the circuit by pass/fail determination for the optimized delay amount. However, the method needs a circuit for the control of the calibration pattern and the pass/fail determination. Such a circuit increases an area for the delay circuit.
Some examples of this kind of related art are disclosed in Patent Documents 1 to 3.    [Patent Document 1] Japanese Patent Laid-Open No. 2005-078547    [Patent Document 2] Japanese Patent Laid-Open No. 2005-276396    [Patent Document 3] Japanese Patent Laid-Open No. 2006-012363